1. Field of the Invention
The invention relates to a switching power supply that carries out current-mode control. In particular, the invention relates to a switching power supply that suppresses subharmonic oscillation of a pulse signal for current-mode control.
2. Description of the Related Art
In a switching power supply in which a switching element turns on and off, an electric current flows on the primary side of an output transformer so that a pulsating flow generated on the secondary side of the output transformer is rectified and output. In such a power supply, there may be a case where subharmonic oscillation of a pulse signal for current-mode control, which drives the switching element by PWM (pulse-width modulation), occurs during current-mode control. To cope with this, there has been proposed a switching power supply that suppresses such subharmonic oscillation (see e.g. Japanese Laid-Open Patent Publication (Kokai) No. 2004-40856).
The above subharmonic oscillation is a phenomenon where a lower frequency than the switching frequency is generated in a case where a power transistor used as a switching element is caused to operate with a duty cycle of not less than 50%. A mechanism for such subharmonic oscillation is that the difference between the initial value and the final value of inductor current flowing through an output transformer, which is connected in series to the power transistor, in each switching cycle increases over time since the rising slope and the falling slope of inductor current do not match during a switching period. The absolute value of the difference between the initial value and the final value of inductor current gradually increases and thereafter decreases upon the lapse of several periods. The repeated increase and decrease of the difference causes oscillation at a low frequency.
Accordingly, in the above switching power supply, the difference between the rising slope and the falling slope of the inductor current is corrected for by a slope compensation signal, and slope compensation is inhibited while the oscillation frequency changes when the power supply is under a light load, whereby the output voltage can be stabilized.
Although in the above switching power supply, the output voltage can be stabilized, since slope compensation is inhibited while the oscillation frequency changes when the switching power supply is under a light load, slope compensation is realized by superimposing (adding) a monotonously increasing slope compensation signal on a detection voltage proportional to inductor current. This may cause a problem, which is described below.
FIG. 6 is a circuit configuration diagram showing an example of a switching power supply that carries out current-mode control. The switching power supply in FIG. 6 is implemented by a flyback DC-DC converter. A switching element turns on and off electric current flowing on the primary side of an output transformer, and a pulsating current generated on the secondary side of the output transformer is rectified and output.
A commercial alternating current with a voltage of 100V is full-wave rectified by a bridge diode BD1. Direct current obtained by the full-wave rectification is smoothed by a capacitor C1 and supplied to a primary winding Tn1 of an output transformer T1 and a series circuit of an N-channel power transistor PT1, which is the switching element. Then, a controller 1, which may be implemented as an integrated circuit, turns on and off the power transistor PT1. A pulsating flow generated in a secondary winding Tn2 of the output transformer T1 is converted into a direct current by a diode D2 and a capacitor C3 and supplied to a load 2.
The output voltage supplied to the load 2 is detected by a voltage detecting circuit (voltage detector) 3, and the detected voltage is input as a feedback signal FB to a feedback terminal Tfb of the controller 1 via a photo-coupler PC1. The controller 1 is also equipped with a power supply terminal Tv to which a power supply voltage Vcc is to be input, a ground terminal Tg of a GND level, an output terminal for a PWM signal, and a current detection terminal Tis to which a current detection signal IS is to be input. A direct current voltage from the bridge diode BD1 is input to the power supply terminal Tv via a resistance R1. Also, a direct current voltage obtained through rectification of an output from an auxiliary winding Tn3 of the output transformer T1 by a diode D1 and a capacitor C2 is input to the power supply terminal Tv. The current detection signal IS, obtained through detection of electric current flowing through the power transistor PT1 by a resistance (current detector) R2, is input to the current detection terminal Tis.
Also, a CR filter comprised of a resistance R3 and a capacitor C4 is interposed between the resistance R2 and the current detection terminal Tis. A detailed description of the CR filter will be given later.
FIG. 7 is a circuit diagram showing a conventional circuit that carries out slope compensation and generates a PWM pulse (PWMPULSE) for driving a power transistor. FIG. 8 shows an example of operational waveforms of the circuit in FIG. 7, and FIG. 9 shows another example of operation waveforms of the circuit in FIG. 7. Where the voltage value of a signal applied to a current detection terminal Tis is Vis, resistances R4 and R5 (resistance values thereof also are denoted by R4 and R5; the same will apply hereinafter) synthesize a slope compensation signal Vsl_in1 and a voltage value Vis to generate a signal Vsl_out. It should be noted that the slope compensation signal Vsl_in1 is generated by an operational amplifier, not shown, and is not affected (interfered with) by the value of the voltage Vis. The amplitude of the signal Vsl_out (which will also be denoted by Vsl_out; the same will apply hereinafter) is expressed by the following equation:Vsl_out=Vsl_in1·R5/(R4+R5)+Vis·R4/(R4+R5)  (1)
FIG. 8 shows waveforms in a case where measures are taken to cope with an ON time reversal phenomenon as disclosed in Japanese Laid-Open Patent Publication (Kokai) No. 2004-40856. FIG. 9 shows waveforms in a case where no measures are taken to cope with an ON time reversal phenomenon as in conventional art disclosed prior to Japanese Laid-Open Patent Publication (Kokai) No. 2004-40856.
The voltage Vis, which is originally a voltage across the resistance R2 shown in FIG. 6, becomes a monotonously increasing signal during a time period Ton during which the power transistor PT1 is on. The waveform of the voltage Vis is the same in FIGS. 8 and 9. The slope compensation signal Vsl_in1 is a signal that monotonously increases during the time period Ton. If measures are taken to cope with an ON time reversal phenomenon, the slope compensation signal Vsl_in1 starts rising in the middle of the time period Ton, as shown in FIG. 8. On the other hand, if no measures are taken to cope with an ON time reversal phenomenon, the slope compensation signal Vsl_in1 starts rising from the beginning of the time period Ton, as shown in FIG. 9.
Then, the signal Vsl_out obtained by weighted addition of the voltage Vis and the slope compensation signal Vs1_in1 in accordance with the above equation (1), is input to the non-inverting input terminal of a PWM comparator PWMCMP. The feedback signal FB, the voltage of which has dropped by an amount equal to the forward voltage of diode D11, is divided by resistances R11 and R12 and input to the inverting input terminal of the PWM comparator PWMCMP. The PWM comparator compares the signal Vsl_out and the dropped feedback signal FB to generate a PWM signal PWMPULSE for turning on and off the power transistor PT1. If the PWM signal PWMPULSE is L (Low), the controller 1 turns on the power transistor PT1, and if the PWM signal PWMPULSE is H (High), the controller 1 turns off the power transistor PT1.
Here, spike noise (a glitch), generated in the voltage Vin upon turning-on the power transistor PT1, presents a problem. FIG. 10 shows the waveform of the voltage Vin with a glitch superimposed thereon. The glitch is also superimposed on the signal Vsl_out in accordance with the above equation (1) and is input to the non-inverting input terminal of the PWM comparator PWMCMP, and hence the PWM comparator PWMCMP may malfunction. Malfunctioning of the PWM comparator presents a more serious problem if an output from the PWM comparator PWMCMP is stored temporarily in a storage device such as a flip-flop and then turning-on/off of the power transistor PT1 is controlled.
To address this problem, the CR filter comprised of the resistance R3 and the capacitor C4 is provided as mentioned above. The CR filter filters spike noise (the glitch) generated in the voltage Vin at turning-on of the power transistor PT1 so as to prevent the PWM comparator from malfunctioning. The time constant of the CR filter is set to, for example, about 1 μs relative to a switching cycle of 10 μs. In this case, the resistance value of the resistance R3 is, for example, 1 kΩ, and the resistance values of the resistances R4 and R5 are 100 kΩ and 2.7 kΩ, respectively.
As described above, if spike noise (a glitch) generated in the voltage Vin at the turning-on of the power transistor PT1 presents a problem, the CR filter comprised of the resistance R3 and the capacitor C4 copes with this problem. However, since the resistance R3 is provided, the resistance R5 substantially changes into a resistance R5+R3 (in the above example, the resistance value changes from 2.7 kΩ to 3.7 kΩ), and as a consequence, the signal Vsl_out also changes in accordance with the above equation (1). In other words, depending on whether the CR filter is present or not, the PWM comparator PWMCMP operates differently with respect to the same signal Vis, and eventually the output voltage value changes. Since the controller 1 is usually constructed as a single integrated circuit (IC), and the CR filter is usually provided as a circuit external to the integrated circuit by a user, it is necessary that the output voltage does not change regardless of whether there is the CR filter or not.
According to claim 4 and Embodiment 3 of Japanese Laid-Open Patent Publication (Kokai) No. 2004-40856 mentioned above, “a signal obtained by superimposing a feedback signal and a slope compensation signal one upon the other” is used, but this configuration presents a problem as described below.
Specifically, a slope compensation signal is added to (superimposed on) a feedback signal of an output voltage. The slope compensation signal, which decreases from an initial positive value value, is generated first and then added to the above-mentioned feedback signal or a current detection signal. For this reason, the circuit configuration is complicated, and the circuit is large in size.
Specifically, generating a signal that decreases from an initial positive (not zero) value to zero is more difficult than generating a signal that monotonously increases from zero. Particularly, in a circuit in which an initial value of current is small and which drains electric charges from a capacitor using a constant current circuit, the voltage across the constant current circuit has to be close to zero. Even if a current mirror circuit is used, the source-to-drain junction enters the nonsaturation region when it comes close to zero, and hence the current mirror circuit cannot function properly. That is, current cannot be constant. Also, the circuit has to be large in size to include a circuit for setting an initial value.